Generally, a placement layout of circuits of a custom VLSI circuit design is created following the completion of the design. The placement can be achieved either graphically or by way of a unique placement routine for each design, e.g., a Cadence Skillcode based routine. If the circuit placement is done graphically, it usually takes a designer some effort to ensure current placement ground rules. Furthermore, if an update is required on either the device size or the topology of the schematic, the placement in the layout must be redone manually. Area, size and form factor of the design are estimated based on the floorplan, the total device width of the schematic, and projected wiring tracks required to route the design. The skill code driven placement usually requires customized functions and hard coded instance names, thereby demanding distinct coding efforts for each macro placement. This provides limited scalability and extensibility, making entries of engineering changes difficult.
In the US Patent Publication No. 7,082,595 to Chan et al., a physical device layout is described providing a schematic that includes circuit data, placement parameters, and defaults. Further inputs include a definition of cell physical position in the horizontal direction, a definition of the cell vertical stacking level, a definition of the cell orientation, a specification of vertical alignment of multiple cell instances, and a definition of vertical spacing between two adjacent cell instances. These input parameters are used to generate a layout with the placement circuit elements.
In the US Patent Publication No. 7,350,174 to Srinivasan et al., a layout synthesis of regular structures using relative placement is described, according to the disclosed layout synthesis relative placement constraint information is received. The relative placement constraint information indicates a relative placement of a plurality of layout objects with respect to each other, wherein one or more of a plurality of layout objects may be at a different level of the layout hierarchy, than a second plurality of layout objects. The plurality of layout objects is then automatically placement according to the relative placement constraint information.